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| rev. 0.1 jan. 2007 preliminary 1 of 59 ddr3 sdram unbuffered dimm * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to ch ange without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, crit ical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any gov- ernmental procurement to which spec ial terms or provisions may apply. ddr3 sdram specification january 2007 revision 0.1
rev. 0.1 jan. 2007 preliminary 2 of 59 ddr3 sdram unbuffered dimm 1.0 ddr2 unbuffered dimm ordering info rmation ............ ................ ................. ................ ............ 4 2.0 key features ......... ................ ................ .............. .............. .............. ............... ............ ........... ....... 4 3.0 address configuration .... ................. ................ ................ ................. ................ ............... ........... 4 4.0 x64 dimm pin configurati ons (front side/back side) .. ............... ................. ................ ............ 5 5.0 x72 dimm pin configurati ons (front side/back side) .. ............... ................. ................ ............ 6 6.0 pin description ............ ................ ................ ................. ................ ................. ............. ................. 7 7.0 input/output functional description ................ .............. .............. ............... .............. .............. .. 8 7.1 address mirroring feature ................ ................ ................ ................. ................ .............. ............ 9 7.1.1 dram pin wiring for mirroring ............. ................. ................ ................. ................ .............. 9 8.0 functional block diagram: ................ ................ ................. ................ ................. ............... ...... 10 8.1 512mb, 64mx64 module(populated as 1 rank of x8 ddr3 sdrams) ................. ............ ........... .......... 10 8.2 512mb, 64mx72 ecc module(populated as 1 rank of x8 ddr3 sdrams) ............... ................ .............11 8.3 1gb, 128mx64 module(populated as 2 ranks of x8 ddr3 sdrams) ................. ............ ........... .......... 12 8.4 1gb, 128mx72 ecc module(populated as 2 ranks of x8 ddr3 sdrams) ............... ................ ............ 13 9.0 absolute maximum ratings ................. ................. ................ ................. ................ ............... .... 14 9.1 absolute maximum dc ratings ................. .............. .............. .............. .............. .............. ............ 14 9.2 dram component operating temperature range ................. ................. .............. .............. ............ 14 10.0 ac & dc operating conditions ..... ................ ................ .............. ............... .............. ............. .14 10.1 recommended dc operating conditions (sstl - 15) ................ ............... .............. ........... .......... 14 10.2 input dc/ac logic level (sstl_15) ................. ................ ................. .............. .............. ............ 15 10.3 differential input cross point voltage ................ ................. .............. .............. .............. ............ 15 10.4 slew rate definition ................. ................ ................ ................. ................ ................. .............. 16 10.4.1 slew rate definition for single-ended signals ................ ............... .............. ........... .......... 16 10.5 slew rate definition for differential signals ................ ................. ................ ................. .............. 17 10.6 output dc and ac output levels .............. ................ ................. ................ ................. .............. 18 10.6.1 differential dc and ac output levels .............. ................. ................ ................. .............. 18 10.6.2 single ende d output slew rate ................. .............. .............. .............. .............. ............ 18 10.6.3 differential output slew rate ............... ................ ................. .............. .............. ............ 19 10.7 default driver characteristics ................. .............. .............. .............. .............. .............. ............ 19 10.8 default driver characteristics ................. .............. .............. .............. .............. .............. ............ 20 10.8.1 default driver characteristics ................. ................. .............. .............. .............. ............ 21 10.9 input/output capacitance ................... ................. .............. .............. .............. .............. ............ 31 11.0 electrical char acteristics and ac timing ........ ................. .............. .............. .............. ............ 32 11.1 refresh parameters by device density ................. .............. .............. .............. .............. ............ 32 11.2 ddr3 sdram standard speed bins a nd trcd, trp and trc for corresponding bin ................ ......... 32 11.3 input clock jitter ................. ................. .............. .............. .............. .............. .............. ............ 34 11.4 timing parameters for ddr3-800 and ddr3-1066 ................ .............. .............. .............. ............ 36 12.0 write leveling ........ ................. ................ ................ ................. ................ ................ ............... 51 13.0 mpr and read leveling .. ................ ................ ................. ................ ................. ............... ...... 54 14.0 physical dimensions : .. ................. ................ ................ ................. ................ ............... ......... 57 14.1 64mbx8 based 64mx64/x72 module(1 rank) ............. ................. ................ ................. .............. 57 14.2 64mbx8 based 128mx64/x72 module(2 ranks) ................. ................. .............. .............. ............ 58 table contents rev. 0.1 jan. 2007 preliminary 3 of 59 ddr3 sdram unbuffered dimm revision history revision month year history 0.0 november 2006 0.1 january 2007 - corrected ac parameter rev. 0.1 jan. 2007 preliminary 4 of 59 ddr3 sdram unbuffered dimm ? jedec standard 1.5v 0.075v power supply ? vddq = 1.5v 0.075v ? 400 mhz f ck for 800mb/sec/pin, 533mhz f ck for 1066mb/sec/pin, 667mhz f ck for 1333mb/sec/pin, 800mhzf ck for 1600mb/sec/pin ? 8 independent internal bank ? programmable cas latency: (4),5,6,7,8,9,10,(11 for high density only) ? posted cas ? programmable additive latency: 0, cl - 2, or cl - 1 clock ? programmable cas write latency(cwl) = 5(ddr3-800), 6(ddr3-1066), 7(ddr3-1333), 8(ddr3-1600) ? 8-bit pre-fetch ? burst length: 8 (interleave without any limit, sequential with st arting address ?000? only), 4 with tccd = 4 which does not al low seamless read or write [either on the fly using a12 or mrs] ? bi-directional differential data strobe ? internal(self) calibration : internal self ca libration through zq pin (rzq : 240 ohm 1%) ? on die termination using odt pin ? average refresh period 7.8us at lower then t case 85 c, 3.9us at 85 c < t case 95 c ? asynchronous reset ? 1066mbps cl7 doesn?t have backward compatibility with 800mbps cl5 speed ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit 5-5-5 e 6-6-6 f 6-6-6 e 7-7-7 f 8-8-8 g 8-8-8 g 9-9-9 h 9-9-9 h 10-10-10 j tck(min) 2.5 1.875 1.5 1.25 ns cas latency 5 6 6 78899 10tck trcd(min) 12.5 15 11.25 13.125 15 12 13.5 11.25 12.5 ns trp(min) 12.5 15 11.25 13.125 15 12 13.5 11.25 12.5 ns tras(min) 37.5 37.5 37.5 37.5 37.5 36 36 35 35 ns trc(min) 50 52.5 48.75 50.625 52.5 48 49.5 46.25 47.25 ns 2.0 key features part number density organization component composition number of rank height m378b6573ez0-ce7/f7/f8/g8 512mb 64mx64 64mx8(k4b510846e-zc##)*8 1 30mm m391b6573ez0-ce7/f7/f8/g8 512mb 64mx72 64mx8(k4b510846e-zc##)*9 1 30mm m378b2973ez0-ce7/f7/f8/g8 1gb 128mx64 64mx8(k4b510846e-zc##)*16 2 30mm m391b2973ez0-ce7/f7/f8/g8 1gb 128mx72 64mx8(k4b510846e-zc##)*18 2 30mm organization row address column address bank address auto precharge 64mx8(512mb) based module a0-a12 a0-a9 ba0-ba2 a10/ap 1.0 ddr3 unbuffered dimm ordering information 3.0 address configuration rev. 0.1 jan. 2007 preliminary 5 of 59 ddr3 sdram unbuffered dimm nc = no connect; nf = no function; nu = not usable; rfu = reserved future use 1. par_in and err_out pins are intended for register control functions (pins 53 and 68) and should not be connected anywhere on the udimm module. 2. nc pins should not be connected to anything, including bussing within the nc group. 3. addresses a3-a8 can be mirrored or not mirrored. please refer to section 7.1 for more information on mirrored addresses. pin front pin back pin front pin back pin front pin back 1 v ref dq 121 v ss 42 nc 162 dqs 17 82 dq33 202 v ss 2 v ss 122 dq4 43 nc 163 v ss 83 v ss 203 dm4,dqs13 3 dq0 123 dq5 44 v ss 164 nc 84 dqs 4 204 dqs 13 4dq1124 v ss 45 nc 165 nc 85 dqs4 205 v ss 5 v ss 125 dm0,dqs9 46 nc 166 v ss 86 v ss 206 dq38 6dqs 0 126 nc,dqs 947 v ss 167 test 87 dq34 207 dq39 7dqs0127 v ss 48 nc 168 reset 88 dq35 208 v ss 8 v ss 128 dq6 key 89 v ss 209 dq44 9 dq2 129 dq7 49 nc 169 cke1 90 dq40 210 dq45 10 dq3 130 v ss 50 cke0 170 v dd 91 dq41 211 v ss 11 v ss 131 dq12 51 v dd 171 a15 92 v ss 212 dm5,dqs14 12 dq8 132 dq13 52 ba2 172 a14 93 dqs 5 213 dqs 14 13 dq9 133 v ss 53 nc, err-out 1 173 v dd 94 dqs5 214 v ss 14 v ss 134 dm1,dqs10 54 v dd 174 a12 95 v ss 215 dq46 15 dqs 1 135 nc,dqs 10 55 a11 175 a9 96 dq42 216 dq47 16 dqs1 136 v ss 56 a7 176 v dd 97 dq43 217 v ss 17 v ss 137 dq14 57 v dd 177 a8 98 v ss 218 dq52 18 dq10 138 dq15 58 a5 178 a6 99 dq48 219 dq53 19 dq11 139 v ss 59 a4 179 v dd 100 dq49 220 v ss 20 v ss 140 dq20 60 v dd 180 a3 101 v ss 221 dm6,dqs15 21 dq16 141 dq21 61 a2 181 a1 102 dqs 6 222 dqs 15 22 dq17 142 v ss 62 v dd 182 v dd 103 dqs6 223 v ss 23 v ss 143 dqs11 63 ck1/nc 183 v dd 104 v ss 224 dq54 24 dqs 2144dqs 11 64 ck 1/nc 184 ck0 105 dq50 225 dq55 25 dqs2 145 v ss 65 v dd 185 ck 0 106 dq51 226 v ss 26 v ss 146 dq22 66 v dd 186 v dd 107 v ss 227 dq60 27 dq18 147 dq23 67 v ref ca 187 nf 108 dq56 228 dq61 28 dq19 148 v ss 68 nc,par_in 1 188 a0 109 dq57 229 v ss 29 v ss 149 dq28 69 v dd 189 v dd 110 v ss 230 dm7,dqs16 30 dq24 150 dq29 70 a10 190 ba1/ba0 111 dqs 7 231 dqs 16 31 dq25 151 v ss 71 ba0/ba1 191 v dd 112 dqs7 232 v ss 32 v ss 152 dm3,dqs12 72 v dd 192 ras 113 v ss 233 dq62 33 dqs 3153dqs 12 73 we 193 s 0 114 dq58 234 dq63 34 dqs3 154 v ss 74 cas 194 v dd 115 dq59 235 v ss 35 v ss 155 dq30 75 v dd 195 odt0 116 v ss 236 v ddspd 36 dq26 156 dq31 76 s 1 196 a13 117 sa0 237 sa1 37 dq27 157 v ss 77 odt1 197 v dd 118 scl 238 sda 38 v ss 158 nc 78 v dd 198 nf 119 v ss 239 v ss 39 nc 159 nc 79 rfuspd 199 v ss 120 v tt 240 v tt 40 nc 160 v ss 80 v ss 200 dq36 41 v ss 161 dm8,dqs17 81 dq32 201 dq37 samsung electronics co., ltd. reserves the right to change products and specifications without notice. 4.0 x64 dimm pin configurati ons (front side/back side) rev. 0.1 jan. 2007 preliminary 6 of 59 ddr3 sdram unbuffered dimm nc = no connect; nf = no function; nu = not usable; rfu = reserved future use 1. par_in and err_out pins are intended for register control functions (pins 53 and 68) and should not be connected anywhere on the udimm module. 2. nc pins should not be connected to anything, including bussing within the nc group. 3. addresses a3-a8 can be mirrored or not mirrored. please refer to section 7.1 for more information on mirrored addresses. pin front pin back pin front pin back pin front pin back 1 v ref dq 121 v ss 42 dqs 8 162 dqs 17 82 dq33 202 v ss 2 v ss 122 dq4 43 dqs8 163 v ss 83 v ss 203 dm4,dqs13 3 dq0 123 dq5 44 v ss 164 cb6 84 dqs 4204dqs 13 4 dq1 124 v ss 45 cb2 165 cb7 85 dqs4 205 v ss 5 v ss 125 dm0,dqs9 46 cb3 166 v ss 86 v ss 206 dq38 6dqs 0 126 nc,dqs 947 v ss 167 test 87 dq34 207 dq39 7 dqs0 127 v ss 48 nc 168 reset 88 dq35 208 v ss 8 v ss 128 dq6 key 89 v ss 209 dq44 9 dq2 129 dq7 49 nc 169 cke1 90 dq40 210 dq45 10 dq3 130 v ss 50 cke0 170 v dd 91 dq41 211 v ss 11 v ss 131 dq12 51 v dd 171 a15 92 v ss 212 dm5,dqs14 12 dq8 132 dq13 52 ba2 172 a14 93 dqs 5213dqs 14 13 dq9 133 v ss 53 nc, err-out 1 173 v dd 94 dqs5 214 v ss 14 v ss 134 dm1,dqs10 54 v dd 174 a12 95 v ss 215 dq46 15 dqs 1 135 nc,dqs 10 55 a11 175 a9 96 dq42 216 dq47 16 dqs1 136 v ss 56 a7 176 v dd 97 dq43 217 v ss 17 v ss 137 dq14 57 v dd 177 a8 98 v ss 218 dq52 18 dq10 138 dq15 58 a5 178 a6 99 dq48 219 dq53 19 dq11 139 v ss 59 a4 179 v dd 100 dq49 220 v ss 20 v ss 140 dq20 60 v dd 180 a3 101 v ss 221 dm6,dqs15 21 dq16 141 dq21 61 a2 181 a1 102 dqs 6222dqs 15 22 dq17 142 v ss 62 v dd 182 v dd 103 dqs6 223 v ss 23 v ss 143 dqs11 63 ck1/nc 183 v dd 104 v ss 224 dq54 24 dqs 2 144 dqs 11 64 ck 1/nc 184 ck0 105 dq50 225 dq55 25 dqs2 145 v ss 65 v dd 185 ck 0 106 dq51 226 v ss 26 v ss 146 dq22 66 v dd 186 v dd 107 v ss 227 dq60 27 dq18 147 dq23 67 v ref ca 187 nf 108 dq56 228 dq61 28 dq19 148 v ss 68 nc,par_in 1 188 a0 109 dq57 229 v ss 29 v ss 149 dq28 69 v dd 189 v dd 110 v ss 230 dm7,dqs16 30 dq24 150 dq29 70 a10 190 ba1/ba0 111 dqs 7231dqs 16 31 dq25 151 v ss 71 ba0/ba1 191 v dd 112 dqs7 232 v ss 32 v ss 152 dm3,dqs12 72 v dd 192 ras 113 v ss 233 dq62 33 dqs 3 153 dqs 12 73 we 193 s 0 114 dq58 234 dq63 34 dqs3 154 v ss 74 cas 194 v dd 115 dq59 235 v ss 35 v ss 155 dq30 75 v dd 195 odt0 116 v ss 236 v ddspd 36 dq26 156 dq31 76 s 1 196 a13 117 sa0 237 sa1 37 dq27 157 v ss 77 odt1 197 v dd 118 scl 238 sda 38 v ss 158 cb4 78 v dd 198 nf 119 v ss 239 v ss 39 cb0 159 cb5 79 rfuspd 199 v ss 120 v tt 240 v tt 40 cb1 160 v ss 80 v ss 200 dq36 41 v ss 161 dm8,dqs17 81 dq32 201 dq37 samsung electronics co., ltd. reserves the right to change products and specifications without notice. 5.0 x72 dimm pin configurati ons (front side/back side) rev. 0.1 jan. 2007 preliminary 7 of 59 ddr3 sdram unbuffered dimm *the vdd and vddq pins are tied common to a single power-plane on these desigus. pin name description pin name description a0-a15 sdram address bus scl i 2 c serial bus clock for eeprom ba0, ba2 sdram bank select sda i 2 c serial bus data line for eeprom ras sdram row address strobe sa0-sa1 i 2 c serial address select for eeprom cas sdram column address strobe v dd * sdram core power supply we sdram wirte enable v ddq * sdram i/o driver power supply s 0, s 1 dimm rank select lines v ref dq sdram i/o reference supply cke0,cke1 sdram clock enable lines v ref ca sdram command/address reference supply odt0, odt1 on-die termination control lines v ss power supply return (ground) dq0 - dq63 dimm memory data bus v dd spd serial eeprom positive power supply cb0 - cb7 dimm ecc check bi ts nc spare pins(no connect) dqs0 - dqs8 sdram data strobes (positive line of differential pair) test used by memory bus analysis tools (unused on memory dimms) dqs 0-dqs 8 sdram differential data strobes (negative line of differential pair) reset set drams known state dm(0-8) sdram data masks/high data strobes (x8-based dimms) nf no function ck0, ck1 sdram clocks (positive line of differential pair) v tt sdram i/o termination supply ck 0, ck 1 sdram clocks (negative line of differential pair) rfu reserved for future use 6.0 pin description rev. 0.1 jan. 2007 preliminary 8 of 59 ddr3 sdram unbuffered dimm symbol type function ck0-ck1 ck 0-ck 1 sstl ck and ck are differential clock inputs. all the ddr3 sdram a ddr/cntl inputs are sampled on the crossing of positive edge of ck and negative edge of ck . output (read) data is reference to the crossing of ck and ck (both directions of crossing) cke0-cke1 sstl activates the sdram ck signal when high and deactivates th e ck signal when low. by deactivating the clocks, cke low initiates the powe down mode, or the self-refresh mode s 0-s 1 sstl enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disbled, new command are ignored but pr evious operations continue. this signal provides for external rank selection on systems with multiple ranks. ras , cas , we sstl ras , cas , and we ( along with s ) define the command being entered. odt0-odt1 sstl when high, termination resistance is enabled for all dq, dqs, dqs and dm pins, assuming the function is enabled in the extended mode register set (emrs). v ref dq supply reference voltage for sstl 15 i/o inputs. v ref ca supply reference voltage for sstl 15 command/address inputs. v ddq supply power supply for the ddr3 sdram output buffers to provide improved noise immunity. for all current ddr3 unbuffered dimm designs, vddq shares the sa me power plane as vdd pins. ba0-ba2 sstl selects which sdram bank of eight is activated. a0-a15 sstl during a bank activate command cycle, addr ess input defines the row address (ra0-ra15) during a read or write command cycle, address input defines the colum address, in addition to the column address, ap is used to invoke autoprecharge operation at the end of the bur st read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1, ba2 defines the bank to be prechar ged. if ap is low, autoprecharge is disbled. during a pre- charge command cycle, ap is used in conjun ction with ba0, ba1, ba2 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0, ba1 or ba2. if ap is low, ba0, ba1 and ba2 are used to define which bank to precharge. dq0-dq63 cb0-cb7 sstl data and check bit input/output pins. dm0-dm8 sstl dm is an input mask signal for write data. input data is mask ed when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. v dd ,v ss supply power and ground for ddr3 sdram input buffers, and core logic. vdd and vddq pins are tied to v dd /v ddq planes on these modules. dqs0-dqs8 dqs 0-dqs 8 sstl data strobe for input and output data. for raw cards using x16 orginized drams, pins dq 0-7 are associated with the ldqs and ldqs pins and pins dq8-15 are associated with udqs and udqs pins. sa0-sa1 - these signals and tied at the system planar to either v ss or v dd spd to configure the serial spd eerpom address range. sda - this bidirectional pin is used to transfer data into or out of the spd eeprom. an external resistor may be connected from the sda bus line to v dd spd to act as a pullup on the system board. scl - this signal is used to clock data into and out of the spd eepr om. an external resistor may be connected from the scl bus time to v dd spd to act as a pullup on the system board. v dd spd supply power supply for spd eeprom. this supply is separate from the v dd /v ddq power plane. eeprom supply is operable from 3.0v to 3.6v. reset - active low asynchronous reset : reset is active when reset is low, and inactive when reset is high. reset must be high during normal operation. reset is a cmos rail to rail signal with dc high and low at 80% and 20% of vdd, i.e. 1.20v for dc high and 0.30v for dc low. 7.0 input/output functional description rev. 0.1 jan. 2007 preliminary 9 of 59 ddr3 sdram unbuffered dimm figure 7.1.1 - wiring differences for mirrored and non-mirrored addresses-no mirroring mirroring since the cross-wired pins have no secondary functions, there is no problem in no rmal operation. any data written is read the s ame way. there are limitations however. when writing to the internal registers with a "load mode" operation, the specific address is requir ed. this requires the controller to know if the rank is mirrored or not. this requires a fewrules. mirroring is done on 2 rank modules and can only be don e on the second rank. there is not a requirement that the seco nd rank be mirrored. there is a bit assignment in the spd that indicates whether the module has been designed with the mirrored feature or not. see the ddr3 udimm spd specifi cation for these details. the controller must read the spd and have the capability of de -mirroring the address when accessing the second rank. there is a via grid located under the drams for wiring the ca si gnals (address, bank address, command, and control lines) to th e dram pins. the length of the traces from the vias to th e drams places limitations on the bandwidth of the module. the shorter these traces, th e higher the bandwidth. to extend the bandwidth of the ca bus for ddr3 modules, a scheme was defined to reduce the length of these traces. the pins on the dram are defined in a manner that allows for these short tr ace lengths. the ca bus pins in columns 2 and 8, ignoring the mechanical support pins , do not have any special functions (secondary functions). this allows the most flexibility with these pins. t hese are address pins a3, a4, a5, a6, a7, a 8 and bank address pins ba0 and ba1. refer to table . rank 0 dram pins are wired strai ght, with no mismatch between the connector pin assignment and th e dram pin assign- ment. some of the rank 1 dram pins are cross wired as defined in the table. pins not listed in the table are wired straight. figure 7.1.1 illustrates the wiring in both th e mirrored and non-mirrored case. the length s of the traces to the dram pins, is obviously shorter. the via grid is smaller as well. connector pin dram pin rank 0 rank 1 a3 a3 a4 a4 a4 a3 a5 a5 a6 a6 a6 a5 a7 a7 a8 a8 a8 a7 ba0 ba0 ba1 ba1 ba1 ba0 7.1.1 dram pin wiring for mirroring 7.1 address mirroring feature rev. 0.1 jan. 2007 preliminary 10 of 59 ddr3 sdram unbuffered dimm s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm nu/ cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relationships must be maintained as shown. 3. dq, dm, dqs/dqs resistors: refer to associated topology diagram. 4. refer to the appropriate clock wiring topology under the dimm wiring details section of this document. a0 serial pd a1 a2 sa0 sa1 gnd scl sda wp v ss d0 - d7 v dd /v ddq d0 - d7 d0 - d7 v ref dq v ddspd spd a0 - a15 a0-a15 : sdrams d0 - d7 ras ras : sdrams d0 - d7 cas cas : sdrams d0 - d7 we we : sdrams d0 - d7 cke0 cke : sdrams d0 - d7 ba0 - ba2 ba0-ba2 : sdrams d0 - d7 odt0 odt : sdrams d0 - d7 v ref ca d0 - d7 ck0 ck : sdrams d0 - d7 8.1 512mb, 64mx64 module (populated as 1 rank of x8 ddr3 sdrams) 8.0 functional block diagram: rev. 0.1 jan. 2007 preliminary 11 of 59 ddr3 sdram unbuffered dimm s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 dqs 8 dqs8 dm8 dm cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 a0 serial pd a1 a2 sa0 sa1 gnd scl sda wp v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 v ref dq v ddspd spd v ref ca d0 - d8 notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relationships must be maintained as shown. 3. dq, cb, dm, dqs/dqs resistors: refer to associated topology diagram. 4. refer to the appropriate clock wiring topology under the dimm wiring details section of this document. a0 - a15 a0-a15 : sdrams d0 - d8 ras ras : sdrams d0 - d8 cas cas : sdrams d0 - d8 we we : sdrams d0 - d8 cke0 cke : sdrams d0 - d8 ba0 - ba2 ba0-ba2 : sdrams d0 - d8 odt0 odt : sdrams d0 - d8 ck0 ck : sdrams d0 - d8 8.2 512mb, 64mx72 ecc module (populated as 1 rank of x8 ddr3 sdrams) rev. 0.1 jan. 2007 preliminary 12 of 59 ddr3 sdram unbuffered dimm s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 s 1 v ss d0 - d15 v dd /v ddq d0 - d15 d0 - d15 v ref dq v ddspd spd a0 - a15 a0-a15 : sdrams d0 - d15 ras ras : sdrams d0 - d15 cas cas : sdrams d0 - d15 we we : sdrams d0 - d15 cke0 cke : sdrams d0 - d7 ba0 - ba2 ba0-ba2 : sdrams d0 - d15 odt0 odt : sdrams d0 - d7 v ref ca d0 - d15 odt1 odt : sdrams d8 - d15 ck0 ck : sdrams d0 - d7 ck1 ck : sdrams d8 - d15 cke1 cke : sdrams d8 - d15 a0 serial pd a1 a2 sa0 sa1 gnd scl sda wp notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relationships must be maintained as shown. 3. dq, dm, dqs/dqs resistors: refer to associated topology diagram. 8.3 1gb, 128mx64 module (populated as 2 ranks of x8 ddr3 sdrams) rev. 0.1 jan. 2007 preliminary 13 of 59 ddr3 sdram unbuffered dimm s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d16 s 1 dqs 8 dqs8 dm8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d17 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 a0 serial pd a1 a2 sa0 sa1 gnd scl sda wp v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 v ref dq v ddspd spd v ref ca d0 - d17 notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relationships must be maintained as shown. 3. dq, cb, dm, dqs/dqs resistors: refer to associated topology diagram. a0 - a15 a0-a15 : sdrams d0 - d17 ras ras : sdrams d0 - d17 cas cas : sdrams d0 - d17 we we : sdrams d0 - d17 cke0 cke : sdrams d0 - d8 ba0 - ba2 ba0-ba2 : sdrams d0 - d17 odt0 odt : sdrams d0 - d8 odt1 odt : sdrams d9 - d17 ck0 ck : sdrams d0 - d8 ck1 ck : sdrams d9 - d17 cke1 cke : sdrams d9 - d17 8.4 1gb, 128mx72 ecc module (populated as 2 ranks of x8 ddr3 sdrams) rev. 0.1 jan. 2007 preliminary 14 of 59 ddr3 sdram unbuffered dimm 9.0 absolute maximum ratings note : 1. stresses greater than those listed under ?absolute maximum ratings? may cause perm anent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicat ed in the operational sections of this s pecification is not implied. exposure to absolute maximum rating conditi ons for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all times; and vref must be not greater than 0.6xvddq, when vdd and vddq a re less than 500mv; vref may be equal to or less than 300mv. symbol parameter rating units notes vdd voltage on vdd pin relative to vss -0.4 v ~ 1.975 v v 1,3 vddq voltage on vddq pin relative to vss -0.4 v ~ 1.975 v v 1,3 v in, v out voltage on any pin relative to vss -0.4 v ~ 1.975 v v 1 t stg storage temperature -55 to +100 c 1, 2 note : 1. operating temperature t oper is the case surface temperature on the center/top side of the dram. for measurement condi tions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatures where all dram specifications will be supported. during operation, t he dram case tem- perature must be maintained between 0-85 c under all operating conditions 3. some applications require operation of the extended temperature range between 85 c and 95 c case temperature. full specifications are guaran- teed in this range, but the fo llowing additional conditions apply: a) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9us. (this double refresh requirement may not apply for some devices.) b) if self-refresh operation is required in the extended temperatur e range. then it is mandatory to either use the manual self- refresh mode with extended temperature range capability (mr2 a6=0 b and mr2 a7 = 1 b ) or enable the auto self-refresh mode (mr2 a6 = 1 b and mr2 a7 = 0 b ). symbol parameter rating unit notes t oper normal operating temperature range 0 to 85 c 1,2 extended temperature range (optional) 85 to 95 c 1,3 9.2 dram component operating temperature range 9.1 absolute maximum dc ratings 10.0 ac & dc operating conditions 10.1 recommended dc operating conditions (sstl - 15) note : 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together. 3. the ac peak niuse on v ref may not allow v ref to deviate from v ref(dc) by more than +/- 1% vdd (for reference : approx. +/- 15mv) 4. for reference : approx. vdd/2 +/- 15mv symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.5 1.575 v 1,2 vddq supply voltage for output 1.425 1.5 1.575 v 1,2 v ref dq(dc ) i/o reference voltage(dq) 0.49*vddq 0.50*vddq 0.51*vddq v 3 v ref ca(dc) i/o reference voltage(cmd/add) 0.49*vddq 0.50*vddq 0.51*vddq v 3 vtt termination voltage 0.49*vddq 0.50*vddq 0.51*vddq v 4 rev. 0.1 jan. 2007 preliminary 15 of 59 ddr3 sdram unbuffered dimm note : 1. for dq and dm, v ref = v refdq . for input only pins except reset, or v ref = v refca 2. see x.x "overshoot and undershoot specifications" on page xxx 3. the ac peak noise on v ref may not allow v ref to deviate from v ref(dc) by more than +/1 1% vdd (for reference : approx. +/- 15mv) 4. for reference : approx. vdd/2 +/- 15mv symbol parameter speed (mtps) min. max. unit notes v ih (dc) dc input logic high 800 vref + 100 tbd mv 1 1066 vref + 100 1333 vref + 100 1600 vref + 100 v il (dc) dc input logic low 800 tbd vref - 100 mv 1 1066 vref - 100 1333 vref - 100 1600 vref - 100 v ih (ac) ac input logic high 800 vref + 175 -mv1,2 1066 vref + 175 1333 vref + 175 1600 vref + 175 v il (ac) ac input logic low 800 - vref - 175 mv 1,2 1066 vref - 175 1333 vref - 175 1600 vref - 175 v ref dq(dc ) i/o reference voltage(dq) 800/1066/1333/1600 0.49*vddq 0.51*vddq v3,4 v ref ca(dc) i/o reference voltage(cmd/add) 800/1066/1333/1600 0.49*vddq 0.51*vddq v3,4 vtt termination voltage 800/1066/1333/1600 0.49*vddq 0.51*vddq v3,4 cross point voltage for differential input signals (ck, dqs) symbol description ddr3-800/1066 ddr3-1333/1600 unit notes min max min max vix differential input cross point voltage relative to vdd/s -150 150 -150 150 mv to guarantee tight setup and hold times as well as output skew parameters with respec t to clock and strobe, each cross point vo ltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements in below tabl e. the differential input cross point voltage vix is measured from the actual cross point of true and complement signal to the midlevel between of vdd and vss. vdd ck , dqs vdd/2 ck, dqs vss v ix v ix v ix 10.2 input dc/ac logic level (sstl_15) 10.3 differential input cross point voltage rev. 0.1 jan. 2007 preliminary 16 of 59 ddr3 sdram unbuffered dimm input slew rate for input setup time (tis) and data setup time (tds) setup (tis and tds) nominal slew rate for a rising signal is def ined as the slew rate between the last crossing of vref and the first crossing of vih(ac)min. setup (tis and tds) nominal slew rate for a falling signal is defined as the slew ra te between the last crossing of vref and the first crossing of vil(ac)max. input slew rate for input hold time (tih) and data hold time (tdh) hold nominal slew rate for a rising signal is defined as the slew rate between the la st crossing of vil(dc)max and the first cr ossing of vref. hold (tih & tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first c rossing of vref notes : this nominal slew rate applies for linear signal waveforms. description measured defined by applicable for from to input slew rate for rising edge vref vih(ac)min vih(ac)min-vref delta trs setup (tis,tds) input slew rate for falling edge vref vil(ac)max vref-vil(ac)max delta tfs input slew rate for rising edge vil(dc)max vref vref-vil(dc)max delta tfh hold (tih,tdh) input slew rate for falling edge vih(dc)min vref vih(dc)min-vref delta trh v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ssq < figure : input slew rate for setup> v swing(max) delta trs delta tfs v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ssq v swing(max) delta trh delta tfh < figure : input slew rate for hold> 10.4.1 slew rate definiti on for single-ended signals 10.4 slew rate definition rev. 0.1 jan. 2007 preliminary 17 of 59 ddr3 sdram unbuffered dimm vddq vihdiffmin v ref vildiffmax vssq v swing(max) delta trdiff delta tfdiff < figure : differential input slew rate definition for dqs,dqs and ck,ck > differential dc and ac input levels note1: the tbd might be changed based on overshoot undershoot values the differential signal (i.e. ck - ck and dqs - dqs ) must be monothonic between these thresholds symbol description ddr3-800/1066 ddr3-1333/1600 unit notes min max min max vihdiff differential input logic high + 200 tbd + 200 tbd mv 1 vildiff differential input logic low tbd - 200 tbd - 200 description measured defined by from to differential input slew rate for rising edge (ck-ck and dqs-dqs ) vildiffmax vihdiffmin vihdiffmin - vildiffmax delta trdiff differential input slew rate for rising edge (ck-ck and dqs-dqs ) vihdiffmin vildiffmax vihdiffmin - vildiffmax delta tfdiff 10.5 slew rate definition for differential signals rev. 0.1 jan. 2007 preliminary 18 of 59 ddr3 sdram unbuffered dimm single ended dc and ac output levels note : 1. the swing of +/-0.1xvddq is based on approximately 50% of the static single ended output high or low swing with a driver imp edance of 40ohms and an effective test load of 25ohms to vtt=vddq/2. symbol parameter ddr3-800/1066/1333/1600 units notes v oh(dc) dc output high measurement level (f or iv curve linearity) 0.8 x vddq v v om(dc) dc output mid measurement level (for iv curve linearity) 0.5 x vddq v v ol(dc) dc output low measurement level (for iv curve linearity) 0.2 x vddq v v oh(ac) ac output high measurement level (for output sr) vtt + 0.1 x vddq v 1 v ol(ac) ac output low measurement level (for output sr) vtt - 0.1 x vddq v 1 with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac) for single ended signals as shown in the below table and figure. output slew rate is verified by design and charac terization, but may not be subject to production test . description measured defined by applicable for from to single ended output slew rate for rising edge vol(ac) voh(ac) voh(ac)-vol(ac) delta trse single ended output slew rate for falling edge voh(ac) vol(ac) voh(ac)-vol(ac) delta tfse parameters ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max single ended output slew rate 2.5 5 2.5 5 2.5 5 tbd 5 v/ns v ddq v oh(ac) v ref v ol(ac) v ssq < figure : input slew rate for setup> delta trs delta tfs 10.6.2 single ended output slew rate note : 1. the swing of +/-0.2xvddq is based on approximately 50% of the st atic differential output high or low swing with a driver imp edance of 40ohms and an effective test load of 25ohms to vtt=vddq/2. symbol parameter ddr3-800/1066/1333/1600 units notes v ohdiff(ac) ac differential output high measurement level (for output sr) +0.2 x vddq v 1 v oldiff(dc) ac differential output low measurement level (for output sr) -0.2 x vddq v 1 10.6.1 differential dc and ac output levels 10.6 output dc and ac output levels rev. 0.1 jan. 2007 preliminary 19 of 59 ddr3 sdram unbuffered dimm with the reference load for timing measurements, output sl ew rate for falling and rising edges is defined and measured between voldiff(ac) and vohdiff(ac) for differential signals as shown in the below table and figure. output slew rate is verified by design and characte rization, but may not be subject to production test description measured defined by applicable for from to differential output slew rate for rising edge voldiff(ac) vohdiff(ac) vohdiff(ac)-voldiff(ac) delta trdiff differential output slew rate for falling edge vohdiff(ac) voldiff(ac) vohdiff(ac)-voldiff(ac) delta tfdiff parameters ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max differential output slew rate 5 10 5 10 5 10 tbd 10 v/ns v ddq v ohdiff(ac) v ref v oldiff(ac) v ssq < figure : input slew rate for setup> delta trdiff delta tfdiff note : 1. vid (ac) specifies the input differential voltage iv tr - v cp i required for switching, where v tr is the true input signal (such as ck, dqs, dqsl or dqsu) and v cp is the complementary input signal (such as ck , dqs , dqsl , or dqsu ). the minimum value is equal to v ih(ac) - vil(ac) . 2. the typical value of v ix (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ix(ac) is expected to track variations in vddq. v ix(ac) indicates the voltage at which differential input signals must cross. 3. this differential input slew rate is measured at ddr3 sdram pins and used as ddr3 sdram test condition. 4. the typical value of v ox (ac) is expected to be about 0.5 * vddq of the transmitting device and v ox(ac) is expected to track variations in vddq. v ox(ac) indicates the voltage at which differential onput signals must cross. symbol parameter/condition min. max. units notes v id (ac) ac differential input voltage 800 ~ 1066 mts 400 v ddq + 0.6 v 1 1333 ~ 1600 mts 350 v ix (ac) ac differential cross point voltage 0.5 * vddq - 0.175 0.5 * vddq + 0.175 v 2 slew_ck differential input slew rate(min) for ck/ck 2 v/ns 3 slew_dqsin differential slew rate(min) for dqs/dqs 2 v/ns 3 v ox (ac) differential ac output cross point voltage 0.5*vddq - tbd 0.5*vddq + tbd v 4 s out _diff differential output slew rate(min) for dqs/dqs 5 tbd v/ns delta s out _diff mismatch of output slew rate between dqs and dqs 0.25 v/ns v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels > 10.7 default driver characteristics 10.6.3 differential output slew rate rev. 0.1 jan. 2007 preliminary 20 of 59 ddr3 sdram unbuffered dimm (idd values are for full operating range of voltage and temperature) symbol conditions max units notes idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t rasmin(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd ma idd1 operating one bank active-read-precharge current ; iout = 0ma; bl = 8, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is same as idd4w tbd ma idd2p precharge power-down current ; all banks idle; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating tbd ma idd2q precharge quiet standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating tbd ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are sw itching; data bus inputs are switching tbd ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating tbd ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are sw itching; data bus inputs are switching tbd ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 8, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t ras- max(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching;data bus inputs are switching tbd ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 8, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is same as idd4w tbd ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and address bus inputs are sw itching; data bus inputs are switching tbd ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating tbd ma idd6et extended temperature range self-refresh current ; ck and ck at 0v; cke 0.2v; other control and address inputs are floating; data bus inputs are floating, pasr disabled, applicable for mr2 setting a6=0 and a7=1 tbd ma idd6tc auto self-refresh current : ck and ck at 0v; cke 0.2v; other control and address inputs are floating; data bus inputs are floating, pasr disabled, applicable when asr is enabled by mr2 setting a6=1 and a7=0 tbd ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0m a; bl = 8, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; tbd ma 10.8 default driver characteristics rev. 0.1 jan. 2007 preliminary 21 of 59 ddr3 sdram unbuffered dimm within the tables provided further down, an overview about the idd measurement conditi ons is provided as follows: table 1 overview of tables providing idd measurement conditions and dram behavior within the tables about idd measurement conditions, the following definitions are used: ? low is defined as v in <= v ilac (max.); high is defined as v in >= v ihac (min.); ? stable is defined as inputs are stable at a high or low level ? floating is defined as inputs are v ref = v ddq / 2 ? switching is defined as descri bed in the following 2 tables. table 2 definition of switching for address and command input signals table 3 definition of switching for data (dq) table number measurement conditions table 5 idd0 and idd1 table 6 idd2n, idd2q, idd2p(0), idd2p(1) table 7 idd3n and idd3p table 8 idd4r, idd4w, idd7 table 10 idd5b table 11 idd6, idd6et switching for address (row, column) and command signals (cs , ras , cas , we ) is defined as: address (row, column): if not otherwise mentioned the inputs are stable at high or low during 4 clocks and change then to the opposite value (e.g. ax ax ax ax ax ax ax ax ax ax ax ax ..... please see ea ch iddx definition for details) bank address: if not otherwise mentioned the bank addresses should be switc hed like the row/ column addresses - please see each iddx definition for details command (cs , ras , cas , we ): define d = {cs , ras , cas , we } := {high, low, low, low} define d = {cs , ras , cas , we } := {high, high,high,high} define command background pattern = d d d d d d d d d d d d ... if other commands are necessary (e.g. act for idd0 or read fo r idd4r) the background pattern command is substituted by the respective cs , ras , cas , we levels of the necessary command. see each iddx definition for details and figures 1,2,3 as examples. switching for data (dq) is defined as data (dq) data dq is changing between high and low every other data transfe r (once per clock) for dq signals, which means that data dq is stable during one clock; see each id dx definition for exceptions from this ru le and for further details. see figures 1,2, 3 as examples. data masking (dm) no switching; dm must be driven low all the time 10.8.1 default driver characteristics rev. 0.1 jan. 2007 preliminary 22 of 59 ddr3 sdram unbuffered dimm table 4 for idd testing the following parameters are utilized. the following conditions apply: 1. idd specifications are tested afte r the device is properly initialized. 2. input slew rate is specified by ac parametric test conditions. 3. idd parameters are specified with odt and output buffer disabled (mr1 bit a12). parameter bin ddr3 800 ddr3 1066 ddr3 1333 ddr3 1600 unit 5-5-5 6-6-6 6-6-6 7-7-7 8-8-8 7-7-7 8-8-8 9-9-9 8-8-8 9-9-9 101010 t ckmin (idd) 2.5 1.875 1.5 1.25 ns cl(idd) 566787898910 t rcdmin (idd) 12.5 15 11.25 13.13 15 10.5 12 13.5 10 11.25 12.5 ns t rcmin (idd) 50 52.5 48.75 50.63 52.50 46.5 48 49.5 45 46.25 47.25 ns t rasmin (idd) 37.5 37.5 37.5 37.5 37.5 36 36 36 35 35 35 ns t rpmin (idd) 12.5 15 11.25 13.13 15 10.5 12 13.5 10 11.25 12.5 ns t faw (idd) x4/x8 40 40 37.5 37.5 37.5 30 30 30 30 30 30 ns x165050505050454545404040ns t rrd (idd) x4/x8 10 10 7.5 7.5 7.5 6.0 6.0 6.0 6.0 6.0 6.0 ns x1610101010107.57.57.57.57.57.5ns t rfc (idd) - 512mb 9090909090909090909090ns t rfc (idd) - 1 gb 110 110 110 110 110 110 110 110 110 110 110 ns t rfc (idd) - 2 gb 160 160 160 160 160 160 160 160 160 160 160 ns t rfc (idd) - 4 gb 300 300 300 300 300 300 300 300 300 300 300 ns rev. 0.1 jan. 2007 preliminary 23 of 59 ddr3 sdram unbuffered dimm table 5 idd measurement conditions for idd0 and idd1 current idd0 idd1 name operating current 0 -> one bank activate -> precharge operating current 1 -> one bank activate -> read -> precharge measurement condition timing diagram example figure 1 cke high high external clock on on t ck t ck min(idd) t ck min(idd) t rc t rc min(idd) t rc min(idd) t ras t ras min(idd) t ras min(idd) t rcd n.a. t rcd min(idd) t rrd n.a. n.a. cl n.a. cl(idd) al n.a. 0 cs high between. activate and precharge commands high between activate, read and precharge command inputs (cs , ras , cas , we ) switching as described in table 2; only exceptions are activate and precharge com- mands; example of idd0 pattern: a0 d d d d d d d d d d d p0 (ddr3-800: tras = 37.5ns between (a)ctivate and (p)recharge to bank 0 ; definition of d and d: see table 2) switching as described in table 2; only exceptions are activate, read and precharge commands; example of idd1 pattern: a0 d d d d r0 d d d dd d d dd d p0 (ddr3-800 -555: trcd = 12.5ns between (a)ctivate and (r)ead to bank 0 ; definition of d and d: see table 2) row, column addresses row addresses switching as described in table 2; address input a10 must be low all the time! row addresses switching as described in table 2; address input a10 must be low all the time! bank addresses bank address is fixed ( bank 0) bank address is fixed (bank 0) data i/o switching as described in table 3 read data: output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to "1". when there is no read data burst from dram the dq i/o should be floating. output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] burst length n.a. 8 fixed / mr0 bits [a1, a0] = {0,0} active banks one act-pre loop one act-rd-pre loop idle banks all other all other precharge power down mode / mode register bit 12 n.a. n.a. rev. 0.1 jan. 2007 preliminary 24 of 59 ddr3 sdram unbuffered dimm t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 ck t17 t18 act 000 idd1 measurement loop ba[2:0] addr_a[9:0] addr_b[10] addr_c[12:11] cs ras cas we cmd dq dm 3ff 000 000 3ff 00 11 00 00 11 000 d d rd d d d d d d d d d pre d d d d d 0 0 1 1 0 0 1 1 figure 1 idd1 example (ddr3-800-555, 512mb x8): data dq is shown but t he output buffer should be switched off (per mr1 bit a12 ="1") to achieve iout = 0ma. address inputs are split into 3 parts. rev. 0.1 jan. 2007 preliminary 25 of 59 ddr3 sdram unbuffered dimm table 6 idd measurement conditions for idd2n, idd2p(1), idd2p(0) and idd2q a. in ddr3 the mrs bit 12 defines dll on/off behavior only for pr echarge power down. there are 2 different precharge power down states possible : one with dll on (fast exit, bit 12 = 1) and one with dll off (slow exit, bit 12 = 0). b. because it is an exit after precharge power down the valid commands are: activate, refresh, mode-register set, enter - self refresh. current idd2n idd2p(1) a idd2p(0) idd2q name precharge standby current precharge power down current fast exit - mrs a12 bit = 1 precharge power down current slow exit - mrs a12 bit = 0 precharge quiet standby current measurement condition timing diagram example figure 2 cke high low low low external clock on on on on t ck t ckmin (idd) t ckmin (idd) t ckmin (idd) t ckmin (idd) t rc n.a. n.a. n.a. n.a. t ras n.a. n.a. n.a. n.a. t rcd n.a. n.a. n.a. n.a. t rrd n.a. n.a. n.a. n.a. cl n.a. n.a. n.a. n.a. al n.a. n.a. n.a. n.a. cs high stable high stable bank address, row addr. and command inputs switching as described in table 2 stable stable stable data inputs switching floating floating floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] disabled / [0,0] disabled / [0,0] burst length n.a. n.a. n.a. n.a. active banks none none none none idle banks all all all all precharge power down mode / mode register bit a n.a. fast exit / 1 (any valid command after txp b ) slow exit / 0 slow exit (rd and odt commands must satisfy txpdll-al) n.a. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 ck 0 idd2n /idd3n measurement loop ba[2:0] addr[12:0] cs ras cas we cmd dq[7:0] dm 7 0 0000 1fff 0000 d d d d figure2 idd2n /idd3n example (ddr3-800-555, 512mb x8) d d d d d d d ff 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 rev. 0.1 jan. 2007 preliminary 26 of 59 ddr3 sdram unbuffered dimm table 7 idd measurement conditions for idd3n and idd3p(fast exit) a. ddr3 will offer only one active power down mode with dll on (-> fast exit). mrs bit 12 will not be used for active power dow n. instead bit 12 will be us ed to switch between 2 different precharge power down modes. current idd3n idd3p name active standby current active power-down current a always fast exit measurement condition timing diagram example figure 2 cke high low external clock on on t ck t ckmin (idd) t ckmin (idd) t rc n.a. n.a. t ras n.a. n.a. t rcd n.a. n.a. t rrd n.a. n.a. cl n.a. n.a. al n.a. n.a. cs high stable addr. and cmd inputs switching as described in table 2 stable data inputs switching as described in table 3 floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] burst length n.a. n.a. active banks all all idle banks none none precharge power down mode / mode register bit a n.a. n.a. (active power down mode is always "fast exit" with dll on rev. 0.1 jan. 2007 preliminary 27 of 59 ddr3 sdram unbuffered dimm table 8 idd measurement conditions for idd4r, idd4w and idd7 current idd4r idd4w idd7 name operating current burst read operating current burst write all bank interleave read current measurement condition timing diagram example figure 3 cke high high high external clock on on on t ck t ckmin (idd) t ckmin (idd) t ckmin (idd) t rc n.a. n.a. t rcmin (idd) t ras n.a. n.a. t rasmin (idd) t rcd n.a. n.a. t rcdmin (idd) t rrd n.a. n.a. t rrdmin (idd) cl cl(idd) cl(idd) cl(idd) al 0 0 t rcdmin -1t ck cs high btw. valid cmds high btw. valid cmds high btw. valid cmds command inputs (cs , ras , cas , we ) switching as described in table 2; exceptions are read commands => idd4r pattern: r0ddd r1ddd r2ddd r3ddd r4 ..... rx = read from bank x; definition of d and d: see table 2 switching as described in table 2; exceptions are write commands => idd4w pattern: w0ddd w1ddd w2ddd w3ddd w4 ... wx = write to bank x; definition of d and d: see table 2 for patterns see table 9 row, column addresses column addresses switching as described in table 2; address input a10 must be low all the time! column addresses switching as described in table 2; address input a10 must be low all the time! stable during deselects bank addresses bank address cycling (0 ->1 -> 2 -> 3 ...) bank address cycling (0 ->1 -> 2 -> 3 ...) bank address cycling (0 ->1 -> 2 -> 3 ...), see pattern in table 9 dq i/o seamless read data burst (bl8): output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to "1". seamless write data burst (bl8): input data switches every clock, which means that write data is stable during one clock cycle. dm is low all the time. read data (bl8): output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to "1". output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] disabled / [0,0] burst length 8 fixed / mr0 bits [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} active banks all all all idle banks none none none precharge power down mode / mode register bit n.a. n.a. n.a. rev. 0.1 jan. 2007 preliminary 28 of 59 ddr3 sdram unbuffered dimm t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 ck 000 start of measurement loop ba[2:0] addr_a[9:0] cs ras cas we cmd[2:0] dq[7:0] dm 001 010 000 3ff 000 rd d d rd figure3 idd4r example (ddr3-800-555, 512mb x8): data dq is shown but the output buffer should be switched off (per mr1 bit a12=1) to achieve i out = 0ma. address inputs are split into 3 parts. d d d rd d d 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff t11 t12 t13 001 3ff addr_b[10] addr_c[12:11] 00 11 00 11 d d rd d ff table 9 idd7 pattern for different speed grades and different trrd, tfaw conditions a. a0 = activation of bank 0; ra0 = read with auto-precharge of bank 0; d = deselect speed bin org. tfaw tfaw trrd trrd idd7 pattern a mb/s [ns] [clk] [ns] [clk] 800 all x4/x8 40 16 10 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 dd a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7d d all x16 50 20 10 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 dd d d d d a4 ra4 d d a5 ra5 d d a6 ra6 dd a7 ra7 d d d d d d 1066 all x4/x8 37.5 20 7.5 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 dd d d d d a4 ra4 d d a5 ra5 d d a6 ra6 dd a7 ra7 d d d d d d all x16 50 27 10 6 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d dd d a3 ra3 d d d d d d d a4 ra4 d d d d a5ra5 d d d d a6 ra6 d d d d a7 ra7 d d d dd d d 1333 all x4/x8 30 20 6 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 dd d d d d a4 ra4 d d a5 ra5 d d a6 ra6 dd a7 ra7 d d d d d d all x16 45 30 7.5 5 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3ra3 d d d d d d d d d d d d d a4 ra4 d d da5 ra5 d d d a6 ra6 d d d a7 ra7 d d d dd d d d d d d d d 1600 all x4/x8 30 24 6 5 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3ra3 d d d d d d d a4 ra4 d d d a5 ra5 d dd a6 ra6 d d d a7 ra7 d d d d d d d all x16 40 32 7.5 6 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d dd d a3 ra3 d d d d d d d d d d d d a4 ra4d d d d a5 ra5 d d d d a6 ra6 d d d d a7ra7 d d d d d d d d d d d d rev. 0.1 jan. 2007 preliminary 29 of 59 ddr3 sdram unbuffered dimm table 10 idd measurement conditions for idd5b current idd5b name burst refresh current measurement condition cke high external clock on t ck t ckmin (idd) t rc n.a. t ras n.a. t rcd n.a. t rrd n.a. t rfc t rfcmin (idd) cl n.a. al n.a. cs high btw. valid cmds addr. and cmd inputs switching data inputs switching output buffer dq,dqs / mr1 bit a12 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] burst length n.a. active banks refresh command every t rfc =t rfc min idle banks none precharge power down mode / mode register bit n.a. rev. 0.1 jan. 2007 preliminary 30 of 59 ddr3 sdram unbuffered dimm table 11 idd measurement conditions for idd6 and idd6et a. this is applicable only for devices wh ich support the extended temperature - refer to the supplier datasheet for availabilit y and values. current idd6 idd6et name self-refresh current normal temperature range tcase = 0 .. 85c self-refresh current extended temperature range a tcase = 0 .. 95c measurement condition temperature tcase = 85c tcase = 95c auto self refresh(asr) / mr2 bit a6 disabled / "0" disabled / "0" self refresh temperature range (srt) / mr2 bit a7 disabled / "0" enabled / "1" cke low low external clock off; ck and ck at low off; ck and ck at low t ck n.a. n.a. t rc n.a. n.a. t ras n.a. n.a. t rcd n.a. n.a. t rrd n.a. n.a. cl n.a. n.a. al n.a. n.a. cs floating floating command inputs (cs , ras , cas , we ) floating floating row, column addresses floating floating bank addresses floating floating data i/o floating floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] burst length n.a. n.a. active banks all during self-refresh ac tions all during self-refresh actions idle banks all btw. self-refresh actions all btw. self-refresh actions precharge power down mode / mode register bit 12 n.a. n.a. rev. 0.1 jan. 2007 preliminary 31 of 59 ddr3 sdram unbuffered dimm note : 1. pin capacitance specs at 100mhz. 2. non-stacked (monolith) ddr3 spec. stacked devices pin parasites are tbd. 3. cdio=cio(dq)-cio(dqs), max delta cio between dqs and dqs noting that this value includes the effect of coupling as well as odt-on and odt-off. 4. cdi_ctrl= ci(ctrl)-cck, ctrl pins defined as odt, cs and c ke, ma pins defined as a0-a15, ba0-ba3 and cmd pins are defined a s ras, cas and we 5. cdi_ma_cmd = ci(ma_cmd)-cck, ctrl pins defined as odt, cs and cke, ma pins defined as a0-a15, ba0-ba3 and cmd pins are defi ned as ras, cas and we 6. absolute value of cck-cck 7. the minimum cck will be same with minimum ci parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units notes min max min max min max min max input capacitance, ck and ck cck tbd 1.60 tbd 1.60 tbd tbd tbd tbd pf 1,2,7 input capacitance delta, ck and ck cdck 0 0.2 0 0.2 tbd tbd tbd tbd pf 1,2,6 input capacitance, all other input-only pins ci tbd 1.5 tbd 1.5 tbd tbd tbd tbd pf 1,2 input capacitance delta, all control input-only pins cdi_ctrl -0.5 0.3 -0.5 0.3 tbd tbd tbd tbd pf 1,2,4 input capacitance delta, all ca and cmd pins cdi_ma_cmd -0.5 0.5 -0.5 0.5 tbd tbd tbd tbd pf 1,2,5 input/output capacitance, dq, dm, dqs, dqs cio 1.5 3.0 1.5 3.0 1.5 2.5 1.5 tbd pf 1,2 input/output capacitance delta, dq, dm, dqs, dqs cdio -0.5 0.3 -0.5 0.3 tbd tbd tbd tbd pf 1,2,3 10.9 input/output capacitance rev. 0.1 jan. 2007 preliminary 32 of 59 ddr3 sdram unbuffered dimm speed ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units note bin (cl - trcd - trp) 5-5-5 6-6-6 6-6-6 7-7-7 8-8-8 8-8-8 9-9-9 9-9-9 10-10-10 parameter min min min min min min min min min cl 5 6 6 7889910 tck trcd 12.5 15 11.25 13.13 15 12 13.5 11.25 12.5 ns trp 12.5 15 11.25 13.13 15 12 13.5 11.25 12.5 ns tras 37.5 37.5 37.5 37.5 37.5 36 36 tbd tbd ns trc 50 52.5 48.75 50.63 52.5 48 49.5 tbd tbd ns trrd [1kb] 10 10 7.5 7.5 7.5 6.0 6.0 6.0 6.0 ns trrd [2kb] 10 10 10 10 10 7.5 7.5 7.5 7.5 ns tfaw [1kb] 40 40 37.5 37.5 37.5 30 30 30 30 ns tfaw [2kb] 50 50 50 50 50 45 45 40 40 ns (0 c rev. 0.1 jan. 2007 preliminary 34 of 59 ddr3 sdram unbuffered dimm tck(avg) is calculated as the average cl ock period across any consecutive 200 cycle window, where each cloc k period is calculat ed from rising edge to rising edge tck(abs) is the absolute clock period, as measured from one rising edge to the next consecutive rising edge note: the jitter specified is a random jitter meeting a gaussian distribution add note for tch(avg) and tcl(avg) tch(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses: tcl(avg) is defined as the average lo w pulse width, as calculated ac ross any consecutive 200 low pulses: add note for tjit(duty) tjit(duty) is defined as the cumulative set of tch jitter and tc l jitter. tch jitter is the largest deviation of any single tc h form tch(avg). tcl jitter is the largest deviation of any single tcl from tcl(avg) tjit(duty) = min/max of {tjit(ch), tjit(cl)}, where: tjit(ch) = {tchi-tch(avg) where i=1 to 200}, tjit(cl) = {tcli-tcl(avg) where i=1 to 200}, parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max average clock period tck(avg) 2500 3333 1875 3333 1500 3333 1250 3333 ps clock period tck(abs) tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ps parameter symbol ddr3-800 ddr3-800 ddr3-800 ddr3-800 units min max min max min max min max clock period jitter tjit(per) -100 100 -90 90 tbd tbd tbd tbd ps clock period jitter during dll lock- ing period tjit(per,lck) -90 90 -80 80 tbd tbd tbd tbd ps cycle to cycle clock period jitter tjit(cc) 200 180 tbd tbd tbd tbd ps cycle to cycle clock period jitter during dll locking period tjit(cc,lck) 180 160 tbd tbd tbd tbd ps cumulative error across 2cycles terr(2per) tbd tbd tbd tbd tbd tbd tbd tbd cumulative error across 3cycles terr(3per) tbd tbd tbd tbd tbd tbd tbd tbd cumulative error across 4cycles terr(4per) tbd tbd tbd tbd tbd tbd tbd tbd cumulative error across 5cycles terr(5per) tbd tbd tbd tbd tbd tbd tbd tbd cumulative error across 6,7,8,9,10 cycles terr(6~10per) tbd tbd tbd tbd tbd tbd tbd tbd cumulative error across 11~50 cycles terr(11~50per) tbd tbd tbd tbd tbd tbd tbd tbd ps average high pulse width tch(avg) 0.47 0.53 0.47 0.53 tbd tbd tbd tbd tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 tbd tbd tbd tbd tck(avg) duty cycle jitter tjit(duty) -100 100 -75 75 tbd tbd tbd tbd ps n j=1 tckj n n=200 n j=1 tchj n x tck(avg) n=200 n j=1 tclj n x tck(avg) n=200 11.3 input clock jitter rev. 0.1 jan. 2007 preliminary 35 of 59 ddr3 sdram unbuffered dimm add note for tjit(per), tjit(per,lck) tjit(per) is defined as the largest deviation of any single tck from tck(avg). tjit(per ) = min/max of {tcki-tck(avg) where i=1 to 200} tjit(per) defines the single period ji tter when the dll is already locked. tjit(per,lck) uses the same def inition for single period jitter, dur ing the dll locking period only. tjit(per) and tjit(per,lck) are not guaranteed through final production testing add note for tjit(cc), tjit(cc,lck) tjit(cc) is defined as the absolute differen ce in clock period between two consecutive cl ock cycles: tjit(cc) = max of {tcki+1 -tcki} tjit(cc) defines the cycle to cycle jitter when the dll is already locked. tjit(cc,lck) uses the same def inition for cycle to c ycle jitter, during the dll locking period only. tjit(cc) and tjit(cc,lck) are not guar anteed through final production testing add note for terr(nper) terr is defined as the cumulative error ac ross n multiple consecutive cycles from tck(avg). this definition is tbd rev. 0.1 jan. 2007 preliminary 36 of 59 ddr3 sdram unbuffered dimm 11.4 timing parameters for ddr3-800 and ddr3-1066 timing parameters by speed bin speed ddr3-800 ddr3-1066 ddr3-1333 units note parameter symbol min max min max min max clock timing minimum clock cycle time (dll off mode) t ck(dll_off) 8 - 8 - 8 - ns 6 average clock period t ck(avg) see speed bins table ps f clock period t ck(abs) tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ps clock period jitter tjit (per) -100 100 -90 90 -80 80 ps clock period jitter during dll locking period tjit (per, lck) -90 90 -80 80 -70 70 ps cycle to cycle period jitter tjit (cc) 200 180 160 ps cycle to cycle period jitte r during dll locking period tjit (cc, lck) 180 160 140 ps cumulative error across 2 cycles t err(2per) tbd tbd tbd tbd tbd tbd ps cumulative error across 3 cycles t err(3per) tbd tbd tbd tbd tbd tbd ps cumulative error across 4 cycles t err(4per) tbd tbd tbd tbd tbd tbd ps cumulative error across 5 cycles t err(5per) tbd tbd tbd tbd tbd tbd ps cumulative error across n = 6, 7, 8, 9, 10 cycles t err(6-10per) tbd tbd tbd tbd tbd tbd ps cumulative error across n = 11, 12, ... 49, 50 cycles t err(11-50per) tbd tbd tbd tbd tbd tbd ps average high pulse width t ch(avg) 0.47 0.53 0.47 0.53 0.47 0.53 t ck(avg) f average low pulse width t cl(avg) 0.47 0.53 0.47 0.53 0.47 0.53 t ck(avg) f duty cycle jitter t jit(duty) -100 100 -75 75 -60 60 ps 22 data timing dqs,dqs to dq skew, per group, per access t dqsq - 200 - 150 - 125 ps 12,13 dq output hold time from dqs, dqs t qh 0.36 - 0.36 - 0.36 - t ck(avg) 12,13 dq low-impedance time from ck, ck t lz(dq) -800 400 -600 300 -500 250 ps 12,13,14 dq high-impedance time from ck, ck t hz(dq) - 400 - 300 - 250 ps 12,13,14 data setup time to dqs, dqs referenced to vih(ac)vil(ac) levels t ds(base) 75 - 25 - tbd - ps d, 17 data hold time to dqs, dqs referenced to vih(ac)vil(ac) levels t dh(base) 150 - 100 - tbd - ps d, 17 dq and dm input pulse width for each input t dipw 0.35 - 0.35 - 0.35 - t ck(avg) data strobe timing dqs, dqs read preamble t rpre 0.9 - 0.9 - 0.9 - t ck 1, 19 dqs, dqs differential read postamble t rpst 0.3 note1 0.3 note1 0.3 note1 t ck 11,12,13 dqs, dqs output high time t qsh 0.38 - 0.38 - 0.38 - t ck(avg) 12,13 dqs, dqs output low time t qsl 0.38 - 0.38 - 0.38 - t ck(avg) 12,13 dqs, dqs write preamble t wpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck 1 dqs, dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 1 dqs, dqs rising edge output access time from rising ck, ck t dqsck -350 350 -265 265 -225 225 ps 12,13 dqs, dqs low-impedance time (referenced from rl-1) t lz(dqs) -800 400 -600 300 -500 250 ps 12,13,14 dqs, dqs high-impedance time (referenced from rl+bl/ 2) t hz(dqs) - 400 - 300 - 250 ps 12,13,14 dqs, dqs differential input low pulse width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs, dqs differential input high pulse width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs, dqs rising edge to ck, ck rising edge t dqss -0.25 0.25 -0.25 0.25 -0.25 0.25 t ck(avg) c dqs,dqs faling edge setup time to ck, ck rising edge t dss 0.2 - 0.2 - 0.2 - t ck(avg) c dqs,dqs faling edge hold time to ck, ck rising edge t dsh 0.2 - 0.2 - 0.2 - t ck(avg) c rev. 0.1 jan. 2007 preliminary 37 of 59 ddr3 sdram unbuffered dimm timing parameters by speed bin (cont.) speed ddr3-800 ddr3-1066 ddr3-1333 units note parameter symbol min max min max min max command and address timing dll locking time t dllk 512 - 512 - 512 - nck internal read command to precharge command delay t rtp max (4t ck ,7.5ns) - max (4t ck ,7.5ns) - max (4t ck ,7.5ns) - e delay from start of internal write transaction to internal read command t wtr max (4t ck ,7.5ns) - max (4t ck ,7.5ns) - max (4t ck ,7.5ns) - e,18 write recovery time t wr 15 - 15 - 15 - ns e mode register set command cycle time t mrd 4 - 4 - 4 - t ck(avg) mode register set command update delay t mod max (12t ck ,15ns) - max (12t ck ,15ns) - max (12t ck ,15ns) - active to precharge command period t ras 37.5 70,000 37.5 70,000 36 70,000 ns e active to active command period for 1kb page size t rrd max (4t ck ,10ns) - max (4t ck ,7.5ns) - max (4t ck ,6ns) - e active to active command period for 2kb page size t rrd max (4t ck ,10ns) - max (4t ck ,10ns) - max (4t ck ,7.5ns) - e four activate window for 1kb page size t faw 40 - 37.5 - 30 - ns e four activate window for 2kb page size t faw 50 - 50 - 45 - ns e command and address setup time to ck, ck referenced to vih(ac) / vil(ac) levels t is(base) 200 - 125 - tbd - ps b,16 command and address hold time from ck, ck referenced to vih(ac) / vil(ac) levels t ih(base) 275 - 200 - tbd - ps b,16 control & address input pulse width for each input t ipw 0.6 - 0.6 - 0.6 - t ck(avg) multi purpose register recovery time t mprr 1 - 1 - 1 - nck 23 refresh timing 512mb refresh to refresh or refresh to active command interval t rfc 90 - 90 - 90 - ns 1gb refresh to refresh or refresh to active command interval t rfc 110 - 110 - 110 - ns 2gb refresh to refresh or refresh to active command interval t rfc 160 - 160 - 160 - ns 4gb refresh to refresh or refresh to active command interval t rfc 300 - 300 - 300 - ns 8gb refresh to refresh or refresh to active command interval t rfc 350 - 350 - 350 - ns average periodic refresh interval (0 c tcase 85 c ) t refi 7.8 7.8 7.8 us average periodic refresh interval (85 c tcase 95 c ) t refi 3.9 3.9 3.9 us calibration timing power-up and reset calibration time t zqiniti 512 - 512 - 512 - t ck normal operation full calibration time t zqoper 256 - 256 - 256 - t ck normal operation short calibration time t zqcs 64 - 64 - 64 - t ck reset timing exit reset from cke high to a valid command t xpr max(5t ck , t rfc + 10ns) - max(5t ck , t rfc + 10ns) - max(5t ck , t rfc + 10ns) - self refresh timing exit self refresh to commands not requiring a locked dll t xs max(5t ck ,t rfc + 10ns) - max(5t ck ,t rfc + 10ns) - max(5t ck ,t rfc + 10ns) - exit self refresh to commands requiring a locked dll t xsdll t dllk (min) - t dllk (min) - t dllk (min) - t ck minimum cke low width for self refresh entry to exit timing t ckesr t cke (min) + 1t ck - t cke (min) + 1t ck - t cke (min) + 1t ck - valid clock requirement after self refresh entry (sre) t cksre max(5t ck ,10ns) - max(5t ck ,10ns) - max(5t ck ,10ns) - valid clock requirement before self refresh exit (srx) t cksrx max(5t ck ,10ns) - max(5t ck ,10ns) - max(5t ck ,10ns) - rev. 0.1 jan. 2007 preliminary 38 of 59 ddr3 sdram unbuffered dimm timing parameters by speed bin (cont.) speed ddr3-800 ddr3-1066 ddr3-1333 units note parameter symbol min max min max min max power down timing exit power down with dll on to any valid command;exit percharge power down with dll frozen to commands not requiring a locked dll t xp max (3t ck ,7.5ns) - max (3t ck ,7.5ns) - max (3t ck ,6ns) - exit precharge power down with dll frozen to commands requiring a locked dll t xpdll max (10t ck ,24ns) - max (10t ck ,24ns) - max (10t ck ,24ns) - 2 cke minimum pulse width t cke max (3t ck ,7.5ns) - max (3t ck ,5.625ns) - max (3t ck ,5.625ns) - command pass disable delay t cpded 1 - 1 - 1 - nck power down entry to exit timing t pd t cke (min) 9*t refi t cke (min) 9*t refi t cke (min) 9*t refi t ck 15 timing of act command to power down entry t actpden 1 - 1 - 1 - nck 20 timing of pre command to power down entry t prpden 1 - 1 - 1 - nck 20 timing of rd/rda command to power down entry t rdpden rl + 4 +1 - rl + 4 +1 - rl + 4 +1 - timing of wr command to power down entry (bl8otf, bl8mrs, bl4otf) t wrpden wl + 4 +(t wr / t ck ) - wl + 4 +(t wr / t ck ) - wl + 4 +(t wr / t ck ) - nck 9 timing of wra command to power down entry (bl8otf, bl8mrs, bl4otf) t wrapden wl + 4 +wr +1 - wl + 4 +wr +1 - wl + 4 +wr +1 - nck 10 timing of wr command to power down entry (bl4mrs) t wrpden wl + 2 +(t wr / t ck ) - wl + 2 +(t wr / t ck ) - wl + 2 +(t wr / t ck ) - nck 9 timing of wra command to power down entry (bl4mrs) t wrapden wl +2 +wr +1 - wl +2 +wr +1 - wl +2 +wr +1 - nck 10 timing of ref command to power down entry t refpden 1 - 1 - 1 - 20,21 timing of mrs command to power down entry t mrspden t mod(min) - t mod(min) - t mod(min) - t ck odt timing odt high time without write command or with wirte com- mand and bc4 odth4 4 - 4 - 4 - nck odt high time with write command and bl8 odth8 6 - 6 - 6 - nck asynchronous rtt tum-on delay (power-down with dll frozen) t aonpd 1 9 1 9 1 9 ns asynchronous rtt tum-off delay (power-down with dll frozen) t aofpd 1 9 1 9 1 9 ns odt turn-on t aon -400 400 -300 30 -250 250 ps 7,12 rtt_nom and rtt_wr turn-off time from odtloff refer- ence t aof 0.3 0.7 0.3 0.7 0.3 0.7 t ck(avg) 8,12 rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 0.3 0.7 t ck(avg) 12 write leveling timing first dqs pulse rising edge after tdqss margining mode is programmed t wlmrd 40 - 40 - 40 - t ck 3 dqs/dqs delay after tdqs margining mode is programmed t wldqsen 25 - 25 - 25 - t ck 3 setup time for tdqss latch t wls 0.15 - 0.15 - 0.15 - t ck(avg) hold time of tdqss latch t wlh 0.15 - 0.15 - 0.15 - t ck(avg) write leveling output delay t wlo 0 9 0 9 0 9 ns write leveling output error t wloe 0 2 0 2 0 2 ns write leveling system specific design guidelines (reference) write leveling window: system clock and strobe signal rout- ing to be matched within tbd t wlw -0.4 0.4 -0.4 0.4 -0.4 0.4 t ck write leveling repetetition time t wlr 16 - 16 - 16 - t ck 3 rev. 0.1 jan. 2007 preliminary 39 of 59 ddr3 sdram unbuffered dimm jitter notes specific note a unit ?tck(avg)? represents the actual tck(avg) of the input cl ock under operation. unit ?nck? represents one clock cycle of the input clock, counting the actual clock edges. ex) tmrd = 4 [nck] means; if one mode register set command is registered at tm, another mode register set command may be regist ered at tm+4, even if (tm+4 - tm) is 4 x tck(avg) + terr(4per),min. specific note b these parameters are measured from a command/address signal (cke, cs , ras , cas , we , odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as the set up and hold are relative to the clock signal crossing that latches the command/address. that is, these parameters should be met whether clo ck jitter is present or not. ex) input setup/hold parameters specifying clock to input relationship; such as, tis(base).tih(base),etc. specific note c these parameters are measured from a data strobe signal (dqs(l/u)/dqs(l/u) ) crossing to its respective clock signal (ck/ck ) crossing. the spec val- ues are not affected by the amount of clock jitter applied (i.e. tj it(per), tjit(cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. ex) the parameters specifying clock to strobe re lationship; such as tdqss, tdss, tdsh, etc. specific note d these parameters are measured from a data signal (dm(l/u), dq(l /u)0, dq(l/u)1, etc.) transition edge to its respective data str obe signal (dqs(l/u)/ dqs(l/u) ) crossing. ex) data input setup/hold parameters specifying strobe to data input relationship; such as,tds(base), tdh(base), etc. specific note e for these parameters, the ddr3 sdram device s upports tnparam [nck] = ru{ tparam [ns] / tc k(avg) [ns] }, which is in clock cycle s, assuming all input clock jitter specifications are satisf ied. for example, the device will support tnrp = ru{trp / tck(avg)}, which is in cl ock cycles, if all input clock jitter specifications are met. this means: for d dr3-800 6-6-6, of which trp = 15ns, the devi ce will support tnrp = ru{trp / tck(avg)} = 6, as long as the input clock jitter specifications are met, i. e. precharge command at tm and active command at tm+6 is valid even if (tm+6 - tm) is less than 15ns due to input clock jitter. ex) most parameters specifying dram core timings; such as trcd, trp, trc, tras, trrd, tfaw, twr, twtr, trtp, etc. specific note f these parameters are specified per their av erage values, however it is understood that the following relationship between the a verage timing and the absolute instantaneous timing holds at all times. (min and max of spec values are to be used for ca lculations in the table belo w.) min and max spec values example: for ddr3-800, tch(abs),min=(0.48x2500ps)-100ps=1100ps , if tch(avg),min=0.48tck(avg) and tjit(duty),min=-100ps parameter symbol min max units absolute clock period tck(abs) tck(avg),min + tjit(per),min tck(avg),max + tjit(per),max ps absolute clock high pulse width tch(abs) tch(avg),min x tck(avg),m in + tjit(duty),min tch(avg),max x tck(avg),max + tjit(duty),max ps absolute clock low pulse width tcl(abs) tcl(a vg),min x tck(avg),min + tjit(duty),min tcl( avg),max x tck(avg),max + tjit(duty),max p s rev. 0.1 jan. 2007 preliminary 40 of 59 ddr3 sdram unbuffered dimm timing parameter notes 1. actual value dependant upon measurement level definitions which are tbd. 2. commands requiring a locked dll are: re ad (and rap) and synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register 5. value must be rounded-up to next higher integer value 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. 7. for definition of rtt turn-on time taon see "device operation" 8. for definition of rtt turn-off time taof see "device operation". 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. 10. wr in clock cycles as programmed in mr0 11. the maximum postamble is bound by thzdqs(max) 12. output timing deratings are relative to the sdram input cloc k. when the device is operated wi th input clock jitter, this pa rameter needs to be derated by tbd 13. value is only valid for ron34 14. single ended signal parameter. refer to chapter rev. 0.1 jan. 2007 preliminary 41 of 59 ddr3 sdram unbuffered dimm address / command setup, hold and derating: for all input signals the total tis (setup time) and tih (hold time ) required is calculated by adding the data sheet tis(base) and tih(base) value (see table 4) to the ? tis and ? tih derating value (see table 5) respectively. example: tis (total setup time) = tis(base) + ? tis setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup (tis ) nominal slew rate for a fa lling signal is defined as the slew rate between the last crossing of vref(dc) and the firs t crossing of vil(ac)max. if the actual signal is always earlie r than the nominal slew rate line between shaded ?vref(dc) to ac region?, us e nominal slew rate for derating value (s ee figure 1). if the actual signal is l ater than the nominal slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac lev el to dc level is used for derating value (see figure 3). hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the fi rst crossing of vref(dc). hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded ?dc to vref (dc) region?, use nominal slew rate for derating value (see figure 2). if the actual signal is earlier than t he nominal slew rate line anywhere between s haded ?dc to vref(dc) region?, the slew r ate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value (see figure 4). for a valid transition the input signal has to remain above/ below vih/il(ac) for some time tvac (see table 6). although for slow slew rates the total setup time might be negat ive (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). for slew rates in between the values listed in table 5, the derating values may obtained by linear interpolation. these values are typicall y not subject to production test. they ar e verified by design and characterization. add/cmd setup and hold base-values for 1v/ns note : ac/dc referenced for 1v/ns dq-slew rate and 2v/ns dqs slew rate [ps] ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 reference tis(base) 200 125 tbd tbd v ih/l(ac) tih(base) 275 200 tbd tbd v ih/l(dc) derating values ddr3-800/1066 tis/tih-ac/dc based required time t vac above vih(ac) {blow vil(ac)} for valid transition ? tis, ? tih derating [ps] ac/dc based a clk,clk differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih cmd/ add slew rate v/ns 2.08850885088509658104661127412084128100 1.559345934593467427550835891689974 1.0000000881616242432344050 0.9-2 -4 -2 -4 -2 -4 6 4 1412202030303846 0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 13 14 26 24 34 40 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 6 10 0.4 -62 -60 -62 -60 -60 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10 slew rate[v/ns] t vac [ps] min max >2.0 75 - 2.0 57 - 1.5 50 - 1.0 38 - 0.9 34 - 0.8 29 - 0.7 22 - 0.6 13 - 0.5 0 - < 0.5 0 - rev. 0.1 jan. 2007 preliminary 42 of 59 ddr3 sdram unbuffered dimm v ss ck ck tds tdh setup slew rate setup slew rate rising signal falling signal delta tf delta tr v ref(dc) - vil(ac)max delta tf = vih(ac)min - v ref(dc) delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate vref to ac region vref to ac region figure - illustration of nominal slew rate and tvac for setup time tds (for dq with respect to strobe) and tis (for add/cmd with resp ect to clock). tis tih tds tdh tis tih tvac tvac note :clock and strobe are drawn on a different time scale. dqs dqs rev. 0.1 jan. 2007 preliminary 43 of 59 ddr3 sdram unbuffered dimm v ss ck ck hold slew rate hold slew rate falling signal rising signal delta tr delta tf v ref(dc) - vil(dc)max delta tr = vih(dc)min - v ref(dc) delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region figure - illustration of nominal slew rate for hold time tdh (for dq with r espect to strobe) and tih (for add/cmd with respect to clock). tis tih tis tih dc to v ref region note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs rev. 0.1 jan. 2007 preliminary 44 of 59 ddr3 sdram unbuffered dimm v ss setup slew rate setup slew rate rising signal falling signal delta tf delta tr tangent line[v ref(dc) - vil(ac)max] delta tf = tangent line[vih(ac)min - v ref(dc) ] delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line figure - illustration of tangent line for setup time tds (for dq with resp ect to strobe) and tis (for add/cmd with respect to clock) ck ck tis tih tis tih tvac note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs rev. 0.1 jan. 2007 preliminary 45 of 59 ddr3 sdram unbuffered dimm v ss hold slew rate delta tf delta tr tangent line [ vih(dc)min - v ref(dc) ] delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - vil(dc)max ] delta tr = rising signal figure - illustration of tangent line for hold time tdh (for dq with re spect to strobe) and tih (for add/cmd with respect to clock) ck ck tis tih tis tih note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs rev. 0.1 jan. 2007 preliminary 46 of 59 ddr3 sdram unbuffered dimm data setup, hold a nd slew rate derating: for all input signals the total tds (setup time) and tdh (hold ti me) required is calculated by adding the data sheet tds(base) and tdh(base) value (see table 1) to the ? tds and ? tdh (see table 2) derating value respectively. ex ample: tds (total setup time) = tds(base) + ? tds. setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the fir st crossing of vih(ac)min. setup (tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the fi rst crossing of vil(ac)max (see figure 1). if the actual signal is always earlier than the nominal slew rate line between shaded ?vref(dc) to ac region?, use nominal slew rate for der- ating value. if the actual signal is later than the nominal slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is u sed for derating value (see figure 3). hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the fi rst crossing of vref(dc). hold (tdh) nominal slew rate for a fallin g signal is defined as the slew rate between the last crossing of vih(dc)min and the f irst crossing of vref(dc) (see figure 2). if the actual signal is always later than the nominal slew rate line between shaded ?dc level to vref(dc) regio n?, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref(dc) region? , the slew rate of a tangent line to the actual signal from the dc level to vref(d c) level is used for derating value (see figure 4). for a valid transition the input signal has to remain abov e/below vih/il(ac) for some time tvac (see table 3). although for slow slew rates the total setup time might be negativ e (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete t he transition and reach vih/il(ac). for slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. these values are typically not subj ect to production test. they are ve rified by design and characterization [ table 53 ] data setup and hold base-value note : ac/dc referenced for 1v/ns dq-slew rate and 2 v/ns dqs slew rate) [ table 54 ] derating values ddr3-800/1066 tis/tih-ac/dc based note : a. cell contents shaded in red are defined as ?not supported?. [ table 55 ] required time t vac above vih(ac) {blow vil(ac)} for valid transition [ps] ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 reference tds(base) 75 25 tbd tbd v ih/l(ac) tdh(base) 150 100 tbd tbd v ih/l(dc) ? tds, ? tdh derating [ps] ac/dc based a dqs,dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh dq slew rate v/ns 2.0885088508850---------- 1.55934593459346745-------- 1.0000000881616 ------ 0.9---2-4-2-46414122220---- 0.8-----6-102-210618142624-- 0.7-------3-85013821182934 0.6---------1-107-21582324 0.5-----------11-16-2-6610 0.4-------------30-26-22-10 slew rate[v/ns] t vac [ps] min max >2.0 75 - 2.0 57 - 1.5 50 - 1.0 38 - 0.9 34 - 0.8 29 - 0.7 22 - 0.6 13 - 0.5 0 - <0.5 0 - rev. 0.1 jan. 2007 preliminary 47 of 59 ddr3 sdram unbuffered dimm v ss ck ck tds tdh setup slew rate setup slew rate rising signal falling signal delta tf delta tr v ref(dc) - vil(ac)max delta tf = vih(ac)min - v ref(dc) delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate vref to ac region vref to ac region figure - illustration of nominal slew rate and tvac for setup time tds (for dq with respect to strobe) and tis (for add/cmd with resp ect to clock). tis tih tds tdh tis tih tvac tvac note :clock and strobe are drawn on a different time scale. dqs dqs rev. 0.1 jan. 2007 preliminary 48 of 59 ddr3 sdram unbuffered dimm v ss ck ck hold slew rate hold slew rate falling signal rising signal delta tr delta tf v ref(dc) - vil(dc)max delta tr = vih(dc)min - v ref(dc) delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region figure - illustration of nominal slew rate for hold time tdh (for dq with r espect to strobe) and tih (for add/cmd with respect to clock). tis tih tis tih dc to v ref region note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs rev. 0.1 jan. 2007 preliminary 49 of 59 ddr3 sdram unbuffered dimm v ss setup slew rate setup slew rate rising signal falling signal delta tf delta tr tangent line[v ref(dc) - vil(ac)max] delta tf = tangent line[vih(ac)min - v ref(dc) ] delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line figure - illustration of tangent line for setup time tds (for dq with resp ect to strobe) and tis (for add/cmd with respect to clock) ck ck tis tih tis tih tvac note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs rev. 0.1 jan. 2007 preliminary 50 of 59 ddr3 sdram unbuffered dimm v ss hold slew rate delta tf delta tr tangent line [ vih(dc)min - v ref(dc) ] delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - vil(dc)max ] delta tr = rising signal figure - illustration of tangent line for hold time tdh (for dq with re spect to strobe) and tih (for add/cmd with respect to clock) ck ck tis tih tis tih note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs rev. 0.1 jan. 2007 preliminary 51 of 59 ddr3 sdram unbuffered dimm signal groups this specification categorizes ddr3 sdram timing-critical signals into four groups. the following table summarizes the signals con- tained in each group. all signal groups, except data, implement a fly-by topology. they sweep from the left side of the module to the right. timing-critical signals signal group signals in group raw card version clock ck0, ck0 a, c, d ck0, ck0 , ck1, ck1 b, e, f data dq, dm, dqs, dqs a, b, c, d, e, f control s0, s1, odt0, odt1, cke0, cke1 b, e, f s0, odt0, cke0 a, c, d address/command add, cmd a, b, c, d, e, f rev. 0.1 jan. 2007 preliminary 52 of 59 ddr3 sdram unbuffered dimm description for better signal integrity, ddr3 memory module adopted fly by topology for the commands, addresse s, control signals and clock s. the fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between clock and stro be at every dram on dimm. it makes it difficult for the controller to maintain tdqs s, tdss and tdsh specification. therefore, the controller should support ?write leveling? in ddr3 sdram to compensate the skew write leveling is a scheme to adjust dqs to ck relationship by the controller, with a simple feedback provided by the dram. the memory controller involved in the leveling must have adjustable delay setting on dqs to align the rising edge of dqs with that of the clock at th e dram pin. dram asyn- chronously feeds back ck, sampled with the rising edge of dqs, through the dq bus. the controller repeatedly delays dqs until a transition from 0 to 1 is detected. the dqs delay est ablished through this exercise would ensure tdqss, tdss and tdsh specification. a conceptual timi ng of this scheme is shown as below write leveling concept diff_ck diff_dqs source diff_ck diff_dqs x 0 0 dq push dqs to capture 0-1 x 1 1 dq transition destination dqs/dqs driven by the controller during leveling mode must be terminated by the dram based on ranks populated. similarly, the dq bus d riven by the dram must also be terminated at the controller. one or more data bits should carry the leveling feedback to the c ontroller across the dram configurations x4,x8 and x16. on a x 16 device, both byte lanes should be leveled independently. therefore, a separate feedbac k mechanism should be availabl e for each byte lane. the upp er data bits should provide the feedback of the upper diff_dqs(diff_udqs) to clock re lationship whereas the lower data bits would indicate the lowe r diff_dqs(diff_ldqs) to clock relationship. dram setting for write leveling & dram termination function in that mode dram enters into write leveling mode if a7 in mr1 set ?high? and after finishing leveling, dram exits from write leveling mo de if a7 in mr1 set ?low? (table1). note that in write leveling mode, only dqs/dqs terminations are activated and deactivated vi a odt pin not like normal operation (table2) table1. mr setting involved in the leveling procedure function mr1 enable disable write leveling enable a7 1 0 output buffer mode (qoff) a12 0 1 d d d d d d d d c o n tro lle r data & strobe (dqs, dqs/dqs#) cmd/addr d d d d d d d d c o n tro lle r data & strobe (dqs, dqs/dqs#) cmd/addr [figure1] cmd/ctrl/clk routing topology in ddr3 module 12.0 write leveling rev. 0.1 jan. 2007 preliminary 53 of 59 ddr3 sdram unbuffered dimm table2. dram termination function in the leveling mode note: in write leveling mode with its output buffer disabled (mr1[bit7] = 1 with mr1[bit12] = 1) all rtt_nom settings are allow ed; in write leveling mode with its output buffer enabled (mr1[bit7] = 1 with mr1[bit12] = 0) only rtt_nom settings of rzq/2, rzq/4 and rzq/6 are allowed. odt pin @dram dqs/dqs termination dqs termination de-asserted off off asserted on off procedure description memory controller initiates leveling mode of all drams by setting bit 7 of mr1 to 1. with entering write leveling mode, the dq pins are in undefined driving mode. during write leveling mode, only nop or deselect co mmands are allowed. since the controller levels one rank at a time, the output of other rank must be disabled by setting mr1 bit a12 to 1. controll er may assert odt after tmod, time at which dram is ready to a ccept the odt signal. controller may drive dqs low and dqs high after a delay of twldqsen, at which time dra m has applied on-die termination on these signals. after tdqsl and twlmrd controller provides a single dqs, dqs edge which is used by the dram to sample ck driven from controller. twlmrd(max) tim- ing is controller dependent. dram samples ck status with rising edge of dqs and provides feedback on all the dq bits asynchronously after twlo timing. there is a dq output uncertainty of twloe defined to allow mismatch on dq bits; there are no read strobes (dqs/dqs ) needed for these dqs. controller samples incoming dq and decides to increment or decrement dqs delay setting and launc hes the next dqs/dqs pulse after some time, which is controller dependent. once a 0 to 1 transition is detected, the controller locks dq s delay setting and write leveling is achieved for the device. the below figure describes detailed timing diagram for over all procedure and the timing parameters are shown in below figure. figure2 : timing details of write leveling sequence [d qs is capturing ck low at t1 and ck high at t2 ] write leveling mode exit the following sequence describes how write leveling mode should be exited: 1. after the last rising strobe (see ~t111) edge stop driving t he strobe signals (see ~t128). note: from now on, dq pins are in undefined driving mode, and will remain undefined, until tmod after the respective mr command (t145) 2. drive odt pin low (tis must be satisfied) and keep it low. (see t128) 3. after the rtt is switched off: disable write level mode via mr command (see t132) 4. after tmod is satisfied (t145), a any valid command may be registered. (mr commands may already be issued after tmrd (t13 6). note *: 1. dram has the option to drive leveling feedback on a prime dq or all dqs. if feedback is driv en only on one dq, the remaining dqs must be driven low as shown in above figure, and mainta ined at this state through out the leveling procedure. 2. mrs : load mr1 to enter write leveling mode 3. nop : nop or deselect 4. diff_dqs is the differential data strobe (dqs-dqs ). timing reference points are the zero cr ossings. dqs is shown with solid line, dqs is shown with dotted line 5. ck/ck : ck is shown with soli d dark line, where as ck is drawn with dotted line. 6. dqs needs to fulfill minimum pulse width requirements tdqsh(min) and tdqsl(min) as defined for regular writes; the max pulse width is system dependent nop nop *3 nop nop nop mrs *2 ck *5 ck cmd odt nop nop nop nop nop nop diff_dqs *4 all dqs/ remaining prime dq *1 dqs tmod twldqsen twlmrd twlo twlh twls twloe twlo tdqsh(min) *6 tdqsl(min) *6 tdqsl(min) tdqsh(min) twls twlh t1 t2 rev. 0.1 jan. 2007 preliminary 54 of 59 ddr3 sdram unbuffered dimm table3. related timing parameters note1: the max values are system dependent. note2: twlomax=9ns for ddr3-800/1066/1333, 7.5ns for ddr3-1600 parameter description target values units min max twlmrd first dqs pulse rising edge after tdqs margining mode is programmed 40 note1 tck tmod mode register set command update delay 12 note1 tck twldqsen dqs/dqs delay after tdqss margining mode is programmed 25 note1 tck twls setup time for tdqss flop measured from diff_ck zero crossing to rising strobe edge (diff_dqs zero crossing) 0.16 note1 tck twlh hold time of tdqss flop measured from rising strobe edge (diff_dqs zero crossing) to diff_ck zero crossing edge 0.16 note1 tck twlo write leveling output delay 0 9/7.5 *2 ns twloe write leveling output error 02ns ck ck cmd odt wloff dqs_dqs t111 t112 t116 t128 t131 t132 t136 t145 ba t is rtt_dqs_dqs odtloff valid valid valid valid rtt_dq dq result = 1 twlo + twloe t mod t mrd figure3 : timing details of write leveling exit related timing parameters mr1 rev. 0.1 jan. 2007 preliminary 55 of 59 ddr3 sdram unbuffered dimm note : 1. burst order bit 0 is assigned to the lsb and burst order bit7 is assigned to the msb of the selected mpr function. 2. bank address ba[2:0] and other addresses except a[2:0] and a12/bc are don?t care for read address. mr3 mpr function burst length read address a[2:0] burst order and data pattern notes a2 a1 a0 100 predefined pattern for system read calibration bl8 000 burst order: 0,1,2,3,4,5,6,7 pre-defined pattern : 0,1,0,1,0,1,0,1 1,2 bc4 000 burst order: 0,1,2,3 pre-defined pattern : 0,1,0,1 1,2 bc4 100 burst order: 4,5,6,7 pre-defined pattern : 0,1,0,1 1,2 101 rfu bl8 000 burst order: 0,1,2,3,4,5,6,7 1,2 bc4 000 burst order: 0,1,2,3 1,2 bc4 100 burst order: 4,5,6,7 1,2 110 rfu bl8 000 burst order: 0,1,2,3,4,5,6,7 1,2 bc4 000 burst order: 0,1,2,3 1,2 bc4 100 burst order: 4,5,6,7 1,2 111 odts bl8 000 burst order: 0,1,2,3,4,5,6,7 1,2 bc4 000 burst order: 0,1,2,3 1,2 bc4 100 burst order: 4,5,6,7 1,2 mpr (multi purpose register) ddr3 sdram has 4 registers (8bits per each r egister) inside dram, called mpr (multi purpose register). mpr can be activated usi ng mr3 and if a2 in mr3 is set 1, the dram internal dataflow is changed from dra m cell array to mpr so user can access (readout only) mpr. each register can be addressed using a1&a0 in mr3. one of application of mpr is read leveling (tbd for 3 registers) in order to do system level read timing calibration based on p redetermined and stan- dardized pattern. all banks should be precharged before access mpr and dram enters mpr mode setting a2 in mr3 to high and selec t 1st register in mpr setting a1=high and a0=low which containing predefined 8bit data pattern for read leveling. now dram internal dataflow is s et to mpr so after waiting tmod which is required time to update dram internal setting, user can readout the predefined 8bit data pattern (0101010 1) with issuing read command. the data will come out after normal read latency. afte r reading predefined data pattern from mrp, dram comes back to n ormal mode with setting a2 in mr3 to low [data coding] note : 1. for mpr output bits defined as rfu, dram must output a logical 0. 2. dram?s supporting the odts feature may not output this code mr3 address mpr function burst data coding condition notes a2 a1 a0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 0 0 predefined pattern 0 1 0 1 0101 for system read leveling 111 odts*1 rfu rfu rfu rfu rfu rfu 0 0 rfu 1,2 rfu rfu rfu rfu rfu rfu 0 1 temp < trip point1 (tj=~tc:85c) 1 rfu rfu rfu rfu rfu rfu 1 0 temp>=trip point2 (tj=~tc:95c) 1 rfu rfu rfu rfu rfu rfu 1 1 tp1(tj=~tc:85c)<=temp rev. 0.1 jan. 2007 preliminary 57 of 59 ddr3 sdram unbuffered dimm t0 ck cmd trp pre mrs tm tm ti ti+1 ti+2 ti+3 ti+4 ti+5 ti+6 ti+7 ti+8 ck rd 1) mrs ba mr3 v mr3 a[1:0] 0 0 2) v a[2] 1 0 3) 0 a[9:3] 0 v 0 a10,ap 0 v 0 a[11] 0 v 0 a12,bc# 0 v 0 a[15:13] 0 v 0 1 dqs,dqs dq tmod tmrd tmprr rl=5 notes : 1) rd with bl8 either by mrs or on the fly 2) memory controller must drive low on a[2:0] 3) a[2]=0 selects lower 4 nibble bits 0...3 4) a[2]=1 selects upper 4 nibble bits 4...7 rd 1) v 0 2) 1 4) v v v v v tccd tmrd rl=5 t0 ck cmd trp pre mrs tm tn ti ti+1 ti+2 ti+3 ti+4 ti+5 ti+6 ti+7 ti+8 ck rd 1) mrs ba mr3 v mr3 a[1:0] 0 0 2) v a[2] 1 1 4) 0 a[9:3] 0 v 0 a10,ap 0 v 0 a[11] 0 v 0 a12,bc# 0 v 0 a[15:13] 0 v 0 1 dqs,dqs dq tmod tmrd tmprr rl=5 notes : 1) rd with bl8 either by mrs or on the fly 2) memory controller must drive low on a[2:0] 3) a[2]=0 selects lower 4 nibble bits 0...3 4) a[2]=1 selects upper 4 nibble bits 4...7 rd 1) v 0 2) 0 3) v v v v v tccd tmrd rl=5 readout of predefined pattern for system read calibration with bc4 (rl=5tck, first lower nibble then upper nibble) readout of predefined pattern for system read calibration with bc4 (rl=5tck, first upper nibble then lower nibble) rev. 0.1 jan. 2007 preliminary 58 of 59 ddr3 sdram unbuffered dimm units : millimeters 133.35 9.50 1.270 0.10 3.18 spd n/a (for x72) 128.95 (2) (4x)3.00 0.1 30.00 0.15 2.50 +0.1/-0 17.30 (for x64) ecc the used device is 64m x8 ddr3 sdram, fbga. ddr3 sdram part no : a b 47.00 71.00 14.1 64mbx8 based 64mx64/x72 module(1 rank) 14.0 physical dimensions : 2.50 2.50 1.00 0.2 0.15 2.50 0.20 detail b 5.00 detail a 1.500.10 0.80 0.05 3.80 2x 2.10 0.15 rev. 0.1 jan. 2007 preliminary 59 of 59 ddr3 sdram unbuffered dimm units : millimeters 133.35 9.50 1.270 0.10 4.00 128.95 (2) 2.50 17.30 n/a (for x64) (for x72) ecc the used device is 64m x8 ddr3 sdram, fbga. ddr3 sdram part no : spd a b 47.00 71.00 n/a (for x72) (for x64) ecc 14.2 64mbx8 based 128mx64/x72 module(2 ranks) (4x)3.00 0.1 30.00 0.15 2.50 +0.1/-0 2.50 1.00 0.2 0.15 2.50 0.20 detail b 5.00 detail a 1.500.10 0.80 0.05 3.80 2x 2.10 0.15 |
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